1. Field of the Invention
The present invention relates to memory devices and, more particularly, to a synchronous non-volatile memory device and to a corresponding working method thereof.
2. Description of the Related Art
One of the main requirements of memory devices is reducing the power consumption as far as possible (especially for use in portable systems, such as mobile phones). The circuit blocks of a memory device that mostly affect the power consumption include, for example, voltage generators, such as charge pumps necessary to provide boosted voltages, and current generators, which provide internal current references.
To reduce power consumption, current and voltage generation circuits are switched on to perform an operation on the memory device during a phase of “activity” and are switched off during a phase of “wait” (or of “stand-by”) of the same.
Considering, for example, a reading operation on asynchronous memory devices, an address (corresponding to a memory location wherein a word to be read is stored) is received from an external source. An Address Transition Detection or ATD circuit detects the reception of the address. The current and voltage generation circuits are switched on in response to the detection of the address to allow the reading of the word. Typically, the current and voltage generation circuits are maintained switched on for a predetermined period far longer than the duration of the reading operation (for example, 600 ns and 40 ns, respectively). This maintains the current and voltage generation circuits in a ready condition in case a new operation must be performed subsequently.
Generally this method of operation is also applied to synchronous memory devices, i.e., memory devices wherein each operation is synchronized with a clock. The synchronous memory devices are implemented in such way to communicate with external devices (for example, a microprocessor that needs to read the data stored in the memory device) through external communication buses.
Let us consider, for example, a synchronous memory device implemented according to a protocol that allows working with a low number of signals so as to limit the corresponding number of pins of the memory device, and therefore cost and size thereof. An example of such protocol is the Low Pin Count (LPC) protocol that provides a communication bus formed by a reduced number of signal lines for transferring address codes (to access memory locations), data (such as words to be read from or to be written onto the memory device) and command codes (to perform a read or write operation on the memory device). The communication bus further provides clock signals and signals corresponding to operation requests. A bus conforming to the standard LPC exploits a time-division multiplexing scheme that allows a transfer parallelism typically lower than that of the memories, which have a plurality of signal lines for the transfer both of the data and of the addresses depending on the sizes of the words and of the memory, respectively (in terms of number of locations).
Typically, an external microprocessor provides an operation request to the synchronous memory device conforming to the LPC protocol, which in response thereto activates the voltage and current generation circuits. Subsequently, during an initial time equal to some clock periods, the memory device receives an operation command code and an address for selecting a location. When the address has been received in full, the requested word can be read and returned to the outside. Subsequently to the completion of the operation, the voltage and current generation circuits are maintained on for a predetermined period (as in the case of the asynchronous memories) waiting for a possible new operation.
The inventors have noticed that the foregoing method of operation is not entirely satisfactory. In fact, the known solution does not exploit the characteristics of the above described synchronous memory device to its optimum performance. Thus, the necessity exists to optimize the enabling and disabling management of the voltage and current generation circuits.